Methods and apparatus for automated circuit design are known in the art. Typically, these aforementioned methods and apparatus generate a layout design by effecting placement and routing of a hardware components specified in a netlist, for example, provided in a hardware description language.
A number of electronic design automation (EDA) software packages are available for computer-aided design of integrated circuits are available, including packages from Magma (Santa Clara, Calif.), Cadence (San Jose, Calif.) and Mentor (Wilsonville, Oreg.).
Typically, placement and routing are carried out in accordance with a number of design goals, including a desire to minimize wire length of conducting connectors between various electronic components, a need to minimize power consumption, a need to minimize congestion, and a need to minimize the area of wafer required to fabricate the device.
Unfortunately, many devices produced using these aforementioned techniques are prone to failure. Thus, devices susceptible to failure may be rejected during the manufacturing process, thereby decreasing yield. It would be highly advantageous to have apparatus and methods for generating layout designs that are less susceptible to device failure, thereby incorporating DFM (design for manufacturing) and DFY (design for yield) considerations into the placement and routing phase of device design.